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74LS197 - 4-STAGE PRESETTABLE RIPPLE COUNTERS

General Description

The LS196 and LS197 are asynchronously presettable decade and binary ripple counters.

The LS196 Decade Counter is partitioned into divide-by-two and divide-by-five sections while the LS197 is partitioned into divide-by-two and divideby-eight sections, with all sections having a separate Clock input.

Key Features

  • 8 NOTES: 1.

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📁 Similar Datasheet

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
74LS190 PRESETTABLE BCD/DECADE UP/DOWN COUNTERS
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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4-STAGE PRESETTABLE RIPPLE COUNTERS The SN54/74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50% duty cycle output. The SN54/74LS197 contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter. Low Power Schottky technology is used to achieve typical count rates of 70 MHz and power dissipation of only 80 mW. Both circuit types have a Master Reset (MR) input which overrides all other inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL) overrides clocked operations and asynchronously loads the data on the Parallel Data inputs (Pn) into the flip-flops.