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MPC9608 - 1:10 LVCMOS Zero Delay Clock Buffer

General Description

The MPC9608 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay.

This enables nested clock designs with near-zero insertion delay.

Key Features

  • MPC9608 www. DataSheet4U. com.
  • 1:10 outputs LVCMOS zero-delay buffer Freescale Semiconductor, Inc.
  • Single 3.3 V supply Supports a clock I/O frequency range of 12.5 to 200 MHz Selectable divide-by-two for one output bank Synchronous output enable control (CLK_STOP) Output tristate control (output high impedance) PLL bypass mode for low frequency system test purpose Supports net.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MPC942C LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC958 LOW VOLTAGE PLL CLOCK DRIVER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC9608 1:10 LVCMOS Zero Delay Clock Buffer The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs. Features MPC9608 www.DataSheet4U.com • 1:10 outputs LVCMOS zero-delay buffer Freescale Semiconductor, Inc... • • • • • • • • • • • Single 3.3 V supply Supports a clock I/O frequency range of 12.