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V54C3256164VBUT - LOW POWER 256Mbit SDRAM

Description

The V54C3256164VBUC/T is a low power four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16.

Features

  • 4 banks x 4Mbit x 16 organization.
  • High speed data transfer rates up to 166 MHz.
  • Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge.
  • Single Pulsed RAS Interface.
  • Data Mask for Read/Write Control.
  • Four Banks controlled by BA0 & BA1.
  • Programmable CAS Latency: 2, 3.
  • Programmable Wrap Sequence: Sequential or Interleave.
  • Programmable Burst Length: 1, 2, 4, 8 for Sequential Type 1, 2, 4, 8 for Interleave Type.
  • Multiple Burs.

📥 Download Datasheet

Datasheet Details

Part number V54C3256164VBUT
Manufacturer Mosel Vitelic Corp
File Size 651.17 KB
Description LOW POWER 256Mbit SDRAM
Datasheet download datasheet V54C3256164VBUT Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOSEL VITELIC V54C3256164VBUC/T LOW POWER 256Mbit SDRAM 3.3 VOLT, 54-BALL SOC BGA 54-PIN TSOPII 16M X 16 PRELIMINARY 6 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) CAS Latency = 3 Clock Access Time (tAC2) CAS Latency = 2 166 MHz 6 ns 5.4 ns 5.4 ns 7PC 143 MHz 7 ns 5.4 ns 5.4 ns 7 143 MHz 7 ns 5.
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