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V53C316405A - 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM

General Description

The V53C316405A is a 4,194,304 x 4 bit highperformance CMOS dynamic random access memory.

The V53C316405A offers Page mode operation with Extended Data Output.

The V53C316405A has asymmetric address, 12-bit row and 10-bit column.

Key Features

  • s 4M x 4-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh and Hidden Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-II s Single +3.3V ± 0.3V Power Supply s TTL Interface.

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Datasheet Details

Part number V53C316405A
Manufacturer Mosel Vitelic Corp
File Size 171.12 KB
Description 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM
Datasheet download datasheet V53C316405A Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOSEL VITELIC V53C316405A 3.3 VOLT 4M x 4 EDO PAGE MODE CMOS DYNAMIC RAM V53C316405A Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 50 50 ns 25 ns 20 ns 84 ns 60 60 ns 30 ns 25 ns 104 ns Features s 4M x 4-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh and Hidden Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-II s Single +3.3V ± 0.3V Power Supply s TTL Interface Description The V53C316405A is a 4,194,304 x 4 bit highperformance CMOS dynamic random access memory.