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PL130-58
High Speed Translator Buffer to PECL
FE AT UR E S
Input clock frequency ≤266 MHz JEDEC standard Differential LVPECL output 70mA typical power supply current 300ps Max. Rise/Fall time 740ps input propagation delay LVCMOS and LVTTL Input compatible Single 2.5V ±5% or 3.3V ±10% power supply
with VEE=0V Available in 8 pin SOP Green/RoHS compliant
Package
PIN CONFIGURATION
(TOP VIEW)
DNC REF-IN
OE DNC
PL130-58
18 27 36 45
SOP-8L
VCC Q QB VEE
DESCRIPTION The PL130-58 is a low cost, high performance, high speed, translator buffer that produces a pair of differential LVPECL outputs from CMOS input. Outputs are JEDEC standard LVPECL signals. The device is targeted for Backplane buffering, data distribution, Fibre Channel and many other applications.
PL130-58 Datasheet
