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SY100S834L - Clock Generation Chip

Download the SY100S834L datasheet PDF. This datasheet also covers the SY100S834 variant, as both devices belong to the same clock generation chip family and are provided as variant models within a single manufacturer datasheet.

Description

The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications.

The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SY100S834-MicrelSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number SY100S834L
Manufacturer Micrel Semiconductor
File Size 177.49 KB
Description Clock Generation Chip
Datasheet download datasheet SY100S834L Datasheet

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Other Datasheets by Micrel Semiconductor

Part Number Description
SY100S834 Clock Generation Chip
SY100S838 CLOCK GENERATION CHIP
SY100S838L CLOCK GENERATION CHIP
SY100S839V CLOCK GENERATION CHIP
SY100S811 SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL

Full PDF Text Transcription

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SY100S834/SY100S834L (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) Clock Generation Chip Precision Edge® General Description The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor.
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