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SY100S317 - TRIPLE 2-WIDE OA/OAI GATE

General Description

s Max.

propagation delay of 900ps s IEE min.

48mA s Extended supply voltage option: VEE = 4.2V to 5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75kΩ input pull-down resistors s Approximately 40% lower power than Fairchild s Function

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Datasheet Details

Part number SY100S317
Manufacturer Micrel Semiconductor
File Size 73.88 KB
Description TRIPLE 2-WIDE OA/OAI GATE
Datasheet download datasheet SY100S317 Datasheet

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Micrel, Inc. TRIPLE 2-WIDE OA/OAI GATE SY100S317 SY100S317 FEATURES DESCRIPTION s Max. propagation delay of 900ps s IEE min. of –48mA s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s Internal 75kΩ input pull-down resistors s Approximately 40% lower power than Fairchild s Function and pinout compatible with Fairchild F100K s Available in 28-pin PLCC package The SY100S317 is a set of ultra-fast, triple 2-wide OR/ AND gates designed for use in high-performance ECL systems. This device offers both true and complement outputs. The inputs on this device have 75kΩ pull-down resistors. BLOCK DIAGRAM Ea D1a D2a D3a D4a Eb D1b D2b D3b D4b Ec D1c D2c D3c D4c PIN NAMES Pin Function Dna – Dnc Data Inputs (n = 1...