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SY100H641 - SINGLE SUPPLY 1:9 PECL-TO-TTL

Download the SY100H641 datasheet PDF. This datasheet also covers the SY10H641 variant, as both devices belong to the same single supply 1:9 pecl-to-ttl family and are provided as variant models within a single manufacturer datasheet.

General Description

The SY10/100H641 are single supply, low skew translating 1:9 clock drivers.

Devices in the MicrelSynergy H600 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance.

Key Features

  • s s s s s s s s s s Input frequencies up to 135MHz PECL-to-TTL version of popular ECLinPS E111 Guaranteed low skew specification Latched input Differential internal design VBB output VECL for single-ended operation.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SY10H641_MicrelSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number SY100H641
Manufacturer Micrel Semiconductor
File Size 113.20 KB
Description SINGLE SUPPLY 1:9 PECL-TO-TTL
Datasheet download datasheet SY100H641 Datasheet

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Other Datasheets by Micrel Semiconductor

Part Number Description
SY100H641A SINGLE SUPPLY 1:9 PECL-TO-TTL
SY100H641L 3.3V SINGLE SUPPLY 1:9 PECL-TO-TTL
SY100H646L 3.3V SINGLE SUPPLY OCTAL PECL/TTL-TO-TTL
SY100H600 9-BIT TTL-TO-ECL
SY100H601 9-BIT ECL-TO-TTL

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com SINGLE SUPPLY 1:9 PECL-TO-TTL ClockWorks™ SY10H641 SY100H641 FEATURES s s s s s s s s s s Input frequencies up to 135MHz PECL-to-TTL version of popular ECLinPS E111 Guaranteed low skew specification Latched input Differential internal design VBB output VECL for single-ended operation DESCRIPTION The SY10/100H641 are single supply, low skew translating 1:9 clock drivers. Devices in the MicrelSynergy H600 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The devices feature a 24mA TTL output stage with AC performance specified into a 50pF load capacitance. A latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the latch is transparent.