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DS26556 - 4-Port Cell/Packet Over T1/E1/J1 Transceiver

Download the DS26556 datasheet PDF. This datasheet also covers the DS2 variant, as both devices belong to the same 4-port cell/packet over t1/e1/j1 transceiver family and are provided as variant models within a single manufacturer datasheet.

General Description

The DS26556 is a quad, software-selectable T1, E1, or J1 transceiver with a cell/packet/TDM interface.

It is composed of four framer/formatters + LIUs, and a UTOPIA (cell), POS-PHY™ (packet), and TDM backplane interface.

Key Features

  • Four Independent, Full-Featured T1/E1/J1 Transceivers UTOPIA 2 and 3 Cell Interface POS-PHY 2 and 3 Packet Interface TDM Backplane Supports TDM Bus Rates from 1.544MHz to 16.384MHz Alarm Detection and Insertion Full-Featured BERT for Each Port AMI, B8ZS, HDB3, NRZ Line Coding Transmit Synchronizer BOC Message Controller (T1) One HDLC Controller per Framer Performance Monitor Counters RAI-CI and AIS-CI Support Internal Clock Generator (CLAD).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS2-655.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Maxim Integrated (now Analog Devices)

Part Number Description
DS26502 T1/E1/J1/64KCC BITS Element
DS26504 T1/E1/J1/64KCC BITS Element
DS26518 single-chip 8-port framer and line interface unit (LIU) combination
DS26519 single-chip 16-port framer and line interface unit (LIU) combination
DS26522 Dual T1/E1/J1 Transceiver
DS26524 Quad T1/E1/J1 Transceiver
DS26528 Octal T1/E1/J1 Transceiver
DS26101 8-Port TDM-to-ATM PHY
DS26102 16-Port TDM-to-ATM PHY
DS26303 Octal Line Interface Unit

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION The DS26556 is a quad, software-selectable T1, E1, or J1 transceiver with a cell/packet/TDM interface. It is composed of four framer/formatters + LIUs, and a UTOPIA (cell), POS-PHY™ (packet), and TDM backplane interface. Each framer has an HDLC controller that can be mapped to any DS0 or FDL (T1)/Sa (E1) bit. The DS26556 also includes full-featured BERT devices per port, and an internal clock adapter useful for creating synchronous, high-frequency backplane timing. The DS26556 is controlled through an 8-bit parallel port that can be configured for nonmultiplexed Intel or Motorola operation.