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P2S28D40CTP - (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM

This page provides the datasheet information for the P2S28D40CTP, a member of the P2S28D30CTP (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM family.

Datasheet Summary

Description

P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals www.DataSheet4U.com are referenced to the rising edge of CLK.

Features

  • - Vdd=Vddq=2.5V+0.2V - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency.
  • 2.0 / 2.5/ 3 (programmable) ; Burst length -.

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Datasheet preview – P2S28D40CTP

Datasheet Details

Part number P2S28D40CTP
Manufacturer MIRA
File Size 301.58 KB
Description (P2S28D30CTP / P2S28D40CTP) 128M Double Data Rate Synchronous DRAM
Datasheet download datasheet P2S28D40CTP Datasheet
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Full PDF Text Transcription

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Deutron Electronics Corp. P2S28D30/40CTP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals www.DataSheet4U.com are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK. The P2S28D30/40CTP achieves very high speed clock rate up to 200 MHz . FEATURES - Vdd=Vddq=2.5V+0.2V - Double data rate architecture ; two data transfers per clock cycle.
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