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DISSECLOENCTTINDUEEVIDCES
ispXPLDTM 5000MX Family
3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family
February 2010
Data Sheet
Features
Flexible Multi-Function Block (MFB) Architecture
• SuperWIDE™ logic (up to 136 inputs) • Arithmetic capability • Single- or Dual-port SRAM • FIFO • Ternary CAM
sysCLOCK™ PLL Timing Control
• Multiply and divide between 1 and 32 • Clock shifting capability • External feedback capability
sysIO™ Interfaces
• LVCMOS 1.8, 2.5, 3.3V – Programmable impedance – Hot-socketing – Flexible bus-maintenance (Pull-up, pulldown, bus-keeper, or none) – Open drain operation
• SSTL 2, 3 (I & II) • HSTL (I, III, IV) • PCI 3.3 • GTL+ • LVDS • LVPECL • LVTTL
Table 1.
ISPXPLD5000MX Datasheet
