8600V - 3.3V In-System Programmable SuperBIG High Density PLD

Lattice Semiconductor

General Description

The ispLSI 8000V Family of Register-Intensive, 3.3V SuperBIG In-System Programmable Logic Devices is based on Big Fast Megablocks of 120 registered macrocells and a Global Routing Plane (GRP) structure interconnecting the Big Fast Megablocks.

Key Features

SuperBIG HIGH.

📥 Download Datasheet

8600V 3.3v in-system programmable superbig high density pld by Lattice Semiconductor - Datasheet Preview

Datasheet Details

Part number	8600V
Manufacturer	Lattice Semiconductor
File Size	333.11 KB
Description	3.3V In-System Programmable SuperBIG High Density PLD
Datasheet	8600V Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
86014012A	High Speed Dual Comparator	National Semiconductor
8608	Amperex Tube	Amperex
8609-348-xxxx	(8609-Series) Standard Male / 3 Row	Framatome Connectors International
8609-396-71-xxxx	(8609-Series) Standard Male / 3 Row	Framatome Connectors International
8609-396-xxxx	(8609-Series) Standard Male / 3 Row	Framatome Connectors International

Other Datasheets by Lattice Semiconductor

Part Number	Description

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

ispLSI 8600V ® 3.3V In-System Programmable SuperBIG™ High Density PLD Features • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — 32,000 PLD Gates/600 Macrocells — 192-264 I/O Pins Supporting 3.3V/2.5V I/O — 864 Registers — High-Speed Global and Big Fast Megablock (BFM) Interconnect — Wide 20-Macrocell Generic Logic Block (GLB) for High Performance — Wide Input Gating (44 Inputs per GLB) for Fast Counters, State Machines, Address Decoders, Etc. — PCB-Efficient Ball Grid Array (BGA) Package Options • HIGH-PERFORMANCE E CMOS TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 8.