L64724
Description
1.2 Typical Application 1.3 Features
Summary L64724 Signal Definitions 2.1 Channel Interface 2.2 Channel Clock Interface 2.3 Phase-Locked Loop (PLL) Interface 2.4 Control Signals Interface 2.5 AGC/Clock Control Interface 2.6 Channel Data Output Interface 2.7 Analog-to-Digital Converter (ADC) Interface 2.8 Microcontroller Interfaceea L64724 Registers 3.1 L64724 Register Overview
3.2 Reset and How it Affects Registers 3.3 Groups 0 and 1: Address Pointer Register 3.4 Group 2: System Mode and System Status Registers 3.5 Group 3: Status Registers 3.6 Group 4: Configuration Registers 3.7 Group 5: Self-Tuning Microcontroller Registers 3.8 Group 6: Reserved (Internal Use Only) 3.9 Group 7: Arbiter Control Register 3.10 Reset Effect on Register Bits 3.11 Internal Data Path Reset Effects
1-1 1-3 1-5
Chapter 2
2-3 2-4 2-4 2-5 2-6 2-6 2-7 2-8
Chapter 3
3-1 3-7 3-8 3-9 3-23 3-33 3-77 3-81 3-81 3-82 3-84
Contents iii
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Chapter 4
Channel Interfaces and Data Control 4.1 Data...
