L64704
Description
1.2 Typical Application 1.3 Features
Summary L64704 Signal Definitions 2.1 Channel Interface 2.2 Channel Clock Recovery 2.3 Channel Data Output Interface 2.4 Phase-Locked Loop Interface 2.5 Carrier Synchronizer Loop Controls 2.6 Microcontroller Interface 2.7 Control Signals L64704 Registers 3.1 L64704 Register Overview
3.1.1 Parallel Host Mode Register Operations 3.1.2 Programming Using the Serial Interface 3.2 Reset and How It Affects Registers 3.3 Group 0, 1 Address Pointer Register 3.4 Group 2 Registers 3.4.1 System Mode Register (SMR) 3.4.2 System Status Register (STS) 3.5 Group 3 Registers 3.5.1 Group 3, APR 0, 1 RS Corrected Error Count 3.5.2 Group 3, APR 2, 3 RS Uncorrected Error Count 3.5.3 Group 3, APR 4, 5 Viterbi Bit Error Count 3.5.4 Group 3, APR 6 Control Input and SNR 3.5.5 Group 3, APR 6, 7 Measured VCO Frequency
1-1 1-3 1-5
Chapter 2
2-3 2-3 2-4 2-5 2-6 2-7 2-9
Chapter 3
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3-2 3-7 3-9 3-9 3-10 3-11 3-11 3-16 3-20 3-21 3-21 3-22 3-22 3-23
Contents
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