Datasheet4U Logo Datasheet4U.com

29104BJA - 2K x 8 Asynchronous CMOS Static RAM

General Description

The HM-65162 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process.

The device utilizes asynchronous circuit design for fast cycle time and ease of use.

Key Features

  • Fast Access Time.
  • 70/90ns Max.
  • Low Standby Current.
  • . . . . .50µA Max.
  • Low Operating Current.
  • . . 70mA Max.
  • Data Retention at 2.0V.
  • . . . .20µA Max.
  • TTL Compatible Inputs and Outputs.
  • JEDEC Approved Pinout (2716, 6116 Type).
  • No Clocks or Strobes Required.
  • Equal Cycle and Access Time.
  • Single 5V Supply.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
2911-05-30I 2900 Series / Microminiature Reed Relays Coto Technology
2911-05-321 Reed Relays Coto Technology
2911-05-xxI 2900 Series / Microminiature Reed Relays Coto Technology
2911-12-xxI 2900 Series / Microminiature Reed Relays Coto Technology
2912A PCM Transmit / Receive Filter Intel

Other Datasheets by Intersil (Renesas)

Part Number Description
29102BJA 2K x 8 CMOS RAM
29103BRA 16K x 1 Asynchronous CMOS Static RAM
29109BRA 16K x 1 Asynchronous CMOS Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HM-65162 March 1997 2K x 8 Asynchronous CMOS Static RAM Description The HM-65162 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAMs, ROMs and EPROMs. The HM-65162 is ideally suited for use in microprocessor based systems with its 8-bit word length organization. The convenient output enable also simplifies the bus interface by allowing the data outputs to be controlled independent of the chip enable.