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X5329 - (X5328 / X5329) CPU Supervisor with 32Kbit SPI EEPROM

Download the X5329 datasheet PDF. This datasheet also covers the X5328 variant, as both devices belong to the same (x5328 / x5329) cpu supervisor with 32kbit spi eeprom family and are provided as variant models within a single manufacturer datasheet.

Description

These devices combine three popular functions, Poweron Reset Control, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package.

This combination lowers system cost, reduces board space requirements, and increases reliability.

Features

  • Low VCC detection and reset assertion.
  • Five standard reset threshold voltages.
  • Re-program low VCC reset threshold voltage using special programming sequence.
  • Reset signal valid to VCC = 1V.
  • Long battery life with low power consumption.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (X5328_IntersilCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number X5329
Manufacturer Intersil (Renesas)
File Size 340.91 KB
Description (X5328 / X5329) CPU Supervisor with 32Kbit SPI EEPROM
Datasheet download datasheet X5329 Datasheet

Full PDF Text Transcription

Click to expand full text
® X5328, X5329 (Replaces X25328, X25329) Data Sheet October 17, 2005 FN8132.1 CPU Supervisor with 32Kbit SPI EEPROM FEATURES • Low VCC detection and reset assertion —Five standard reset threshold voltages —Re-program low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Long battery life with low power consumption —<1µA max standby current —<400µA max active current during read • 32Kbits of EEPROM • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2 or all of EEPROM array with Block Lock™ protection —In circuit programmable ROM mode • 2MHz SPI interface modes (0,0 & 1,1) • Minimize EEPROM programming time —32-byte page write mode —Self-timed write cycle —5ms write cycle time (typical) • 2.
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