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MP82C55A - CMOS Programmable Peripheral Interface

General Description

SYMBOL VCC GND D0-D7 RESET CS RD WR A0-A1 www.DataSheet4U.com I/O I I I I I TYPE DESCRIPTION VCC: The +5V power supply pin.

A 0.1µF capacitor between VCC and GND is recommended for decoupling.

GROUND DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.

Key Features

  • as the X82C55 with the exception of no bus hold devices on the port pins. It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in two groups of www. DataSheet4U. com 12 and used in three major modes of operation. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors. Static CMOS circuit design insures low op.

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Other Datasheets by Intersil (now Renesas)

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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® MS82C55A, MQ82C55A, MP82C55A Data Sheet June 15, 2006 FN6140.2 CMOS Programmable Peripheral Interface The Intersil 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The MX82C55A has identical features as the X82C55 with the exception of no bus hold devices on the port pins. It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in two groups of www.DataSheet4U.com 12 and used in three major modes of operation. The high performance and industry standard configuration of the 82C55A make it compatible with the 80C86, 80C88 and other microprocessors.