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CD4085BMS - CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate

General Description

of ‘B’ Series CMOS Devices” A1 1 B1 2 E1 = INHI + A1B1 + C1D1 3 E2 = INH2 + A2B2 + C2D2 4 A2 5 B2 6 VSS 7 14 VDD 13 D1 12 C1 11 INHIBIT 2 10 INHIBIT 1 9 D2 8 C2 Functional Diagram INHIBIT 1 10 Description CD4085BMS contains a pair of AND-OR-INVERT gates, each consisting of two 2 input AND gates

Key Features

  • High Voltage Type (20V Rating).
  • Medium Speed Operation - tPHL = 90ns - tPLH = 125ns (Typ. ) at 10V.
  • Individual Inhibit Controls.
  • 5V, 10V and 15V Parametric Ratings.
  • Standardized Symmetrical Output Characteristics.
  • 100% Tested for Quiescent Current at 20V.
  • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC.
  • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD4085BMS December 1992 CMOS Dual 2 Wide 2 Input AND-OR-INVERT Gate Pinout CD4085BMS TOP VIEW Features • High Voltage Type (20V Rating) • Medium Speed Operation - tPHL = 90ns - tPLH = 125ns (Typ.) at 10V • Individual Inhibit Controls • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No.