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28F008SA-L 8-MBIT (1 MBIT x 8) FLASHFILE TM MEMORY
Y
High-Density Symmetrically-Blocked Architecture Sixteen 64-Kbyte Blocks Low-Voltage Operation b 3 3V g 0 3V or 5 0V g 10% VCC Extended Cycling Capability 10 000 Block Erase Cycles 160 000 Block Erase Cycles per Chip Automated Byte Write and Block Erase Command User Interface Status Register System Performance Enhancements RY BY Status Output Erase Suspend Capability
Y
High-Performance Read 200 ns Maximum Access Time Deep Power-Down Mode 0 20 mA ICC Typical SRAM-Compatible Write Interface Hardware Data Protection Feature Erase Write Lockout during Power Transitions Industry Standard Packaging 40-Lead TSOP 44-Lead PSOP ETOX TM III Nonvolatile Flash Technology 12V Byte Write Block Erase
Y
Y
Y Y
Y
Y Y
Y
Y
Intel’s 28F008SA-L 8 Mbit
28F008SA-L Datasheet
