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IS61VPD25636A - 256K x 36/ 512K x 18 9Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM

This page provides the datasheet information for the IS61VPD25636A, a member of the IS61LPD25636A 256K x 36/ 512K x 18 9Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM family.

Datasheet Summary

Description

are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.

Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • Auto Power-down during deselect.
  • Double cycle deselect.
  • Snooze MODE for reduced-power standby.
  • JTAG Boundary Scan for.

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Datasheet preview – IS61VPD25636A

Datasheet Details

Part number IS61VPD25636A
Manufacturer Integrated Silicon Solution
File Size 253.24 KB
Description 256K x 36/ 512K x 18 9Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
Datasheet download datasheet IS61VPD25636A Datasheet
Additional preview pages of the IS61VPD25636A datasheet.

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Full PDF Text Transcription

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IS61VPD25636A IS61LPD25636A IS61VPD51218A IS61LPD51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM www.DataSheet4U.com ISSI MAY 2005 ® FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Double cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LPD: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VPD: VDD 2.5V + 5%, VDDQ 2.
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