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IS61NSCS25672 - Synchronous SRAM

Description

Because SigmaRAM is a synchronous device, address, data Inputs, and read/write control inputs are captured on the rising edge of the input clock.

Write cycles are internally self-timed and initiated by the rising edge of the clock input.

Features

  • JEDEC SigmaRam pinout and package standard.
  • Single 1.8V power supply (VCC): 1.7V (min) to 1.9V (max).
  • Dedicated output supply voltage (VCCQ): 1.8V or 1.5V typical.
  • LVCMOS-compatible I/O interface.
  • Common data I/O pins (DQs).
  • Single Data Rate (SDR) data transfers.
  • Pipelined (PL) read operations.
  • Double Late Write (DLW) write operations.
  • Burst and non-burst read and write operations, selectable via dedicated control.

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Other Datasheets by ISSI (now Infineon)

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61NSCS25672 IS61NSCS51236 Σ RAM 256K x 72, 512K x 36 Features • JEDEC SigmaRam pinout and package standard • Single 1.8V power supply (VCC): 1.7V (min) to 1.9V (max) • Dedicated output supply voltage (VCCQ): 1.8V or 1.
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