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IS61DDP2B251236A1 - 18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM

Download the IS61DDP2B251236A1 datasheet PDF. This datasheet also covers the IS61DDP2B21M18A variant, as both devices belong to the same 18mb ddr-iip (burst 2) cio synchronous sram family and are provided as variant models within a single manufacturer datasheet.

General Description

512Kx36 and 1Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Common I/O read and write ports.

Synchronous pipeline read with self-timed late write operation.

Double Data Rate (DDR) interface for read and write input ports.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDP2B21M18A-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDP2B21M36C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDP2B21M36C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDP2B21M36C2 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDP2B22M18C 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDP2B22M18C1 36Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDP2B251236A 18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDP2B251236A2 18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDP2B21M18A 18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDP2B21M18A1 18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDP2B21M18A2 18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61DDP2B21M18A/A1/A2 IS61DDP2B251236A/A1/A2 1Mx18, 512Kx36 18Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) ADVANCED INFORMATION JULY 2012 FEATURES DESCRIPTION  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.