IS43R16800CC Datasheet PDF - Integrated Silicon Solution 128Mb DDR Synchronous DRAM Specs

IS43R16800CC - 128Mb DDR Synchronous DRAM

Datasheet Summary

Description

IS43R16800CC is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Features

Vdd =Vddq = 2.5V+0.2V (-5, -6, -75).
Double data rate architecture; two data transfers per clock cycle.
Bidirectional , data strobe (DQS) is transmitted/ received with data.
Differential clock input (CLK and /CLK).
DLL aligns DQ and DQS transitions with CLK transitions edges of DQS.
Commands entered on each positive CLK edge;.
Data and data mask referenced to both edges of DQS.
4 bank operation controlled by BA0 ,.

Datasheet Details

Part number	IS43R16800CC
Manufacturer	Integrated Silicon Solution
File Size	611.71 KB
Description	128Mb DDR Synchronous DRAM
Datasheet	IS43R16800CC Datasheet
Additional preview pages of the IS43R16800CC datasheet.

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Full PDF Text Transcription

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IS43R16800CC 8Mx16 128Mb DDR Synchronous DRAM JUNE 2009 FEATURES: • Vdd =Vddq = 2.5V+0.2V (-5, -6, -75) • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK) • DLL aligns DQ and DQS transitions with CLK transitions edges of DQS • Commands entered on each positive CLK edge; • Data and data mask referenced to both edges of DQS • 4 bank operation controlled by BA0 , BA1 (Bank Address) • /CAS latency -2.0 / 2.5 / 3.

Published: Jul 25, 2016 |