IS43R16320D Datasheet PDF - Integrated Silicon Solution 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM Specs

IS43R16320D - 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM

This page provides the datasheet information for the IS43R16320D, a member of the IS43R86400D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM family.

Datasheet Summary

Description

x8 A0-A12 A0-A9, A11 BA0, BA1 DQ0 DQ7 CK, CK CKE CS CAS RAS WE Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Column Address Strobe Command Row Address Strobe Command Write Enable DM DQS VDD VDDQ VSS VSSQ VREF NC Data Writ

Features

VDD and VDDQ: 2.5V ± 0.2V (-6) VDD and VDDQ: 2.6V ± 0.1V (-5) SSTL_2 compatible I/O Double-data rate architecture; two data transfers per clock cycle Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for READs and centr.

Datasheet Details

Part number	IS43R16320D
Manufacturer	Integrated Silicon Solution
File Size	966.71 KB
Description	16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM
Datasheet	IS43R16320D Datasheet
Additional preview pages of the IS43R16320D datasheet.

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Full PDF Text Transcription

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IS43/46R86400D IS43/46R16320D, IS43/46R32160D NOVEMBER 2012 16Mx32, 32Mx16, 64Mx8 512Mb DDR SDRAM FEATURES • • • • • • • • • • • • • • • • • VDD and VDDQ: 2.5V ± 0.2V (-6) VDD and VDDQ: 2.6V ± 0.1V (-5) SSTL_2 compatible I/O Double-data rate architecture; two data transfers per clock cycle Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs Differential clock inputs (CK and CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Four internal banks for concurrent operation Data Mask for write data.

Published: Aug 11, 2014 |