IS42VS16100C1 Datasheet PDF - Integrated Silicon Solution 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM Specs

IS42VS16100C1 - 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

Datasheet Summary

Description

organized as a 524,288-word x 16-bit x 2-bank for improved performance.

The synchronous DRAMs achieve high-speed data transfer using pipeline architecture.

All inputs and outputs signals refer to the rising edge of the clock input.

Features

Clock frequency: 100 MHz.
Fully synchronous; all signals referenced to a positive clock edge.
Two banks can be operated simultaneously and independently.
Dual internal bank controlled by A11 (bank select).
Single 1.8V power supply.
LVTTL interface.
Programmable burst length.
(1, 2, 4, 8, full page).
Programmable burst sequence: Sequential/Interleave.
2048 refresh cycles every 32 ms.
Random column.

Datasheet Details

Part number	IS42VS16100C1
Manufacturer	Integrated Silicon Solution
File Size	837.26 KB
Description	512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
Datasheet	IS42VS16100C1 Datasheet
Additional preview pages of the IS42VS16100C1 datasheet.

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Full PDF Text Transcription

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IS42VS16100C1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11 (bank select) • Single 1.8V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • 2048 refresh cycles every 32 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Package 400-mil 50-pin TSOP II • Lead-free package option www.

Published: Apr 22, 2010 |