IDT23S05 Datasheet PDF - Integrated Device 3.3V ZERO DELAY CLOCK BUFFER Specs

IDT23S05 - 3.3V ZERO DELAY CLOCK BUFFER

Datasheet Summary

Description

The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

Features

Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs Zero Input-Output Delay Output Skew < 250ps Low jitter.

Datasheet Details

Part number	IDT23S05
Manufacturer	Integrated Device
File Size	62.90 KB
Description	3.3V ZERO DELAY CLOCK BUFFER
Datasheet	IDT23S05 Datasheet
Additional preview pages of the IDT23S05 datasheet.

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Full PDF Text Transcription

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IDT23S05 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE FEATURES: • • • • • • • • • • • • • Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs Zero Input-Output Delay Output Skew < 250ps Low jitter <200 ps cycle-to-cycle IDT23S05-1 for Standard Drive IDT23S05-1H for High Drive No external RC network required Operates at 3.3V VDD Power down mode Spread spectrum compatible Available in SOIC package IDT23S05 DESCRIPTION: The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

Published: Apr 27, 2005 |