IDT74FCT388915T100 Datasheet PDF - Integrated Device Technology 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) Specs

IDT74FCT388915T100 - 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)

This page provides the datasheet information for the IDT74FCT388915T100, a member of the IDT-74FCT 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) family.

Datasheet Summary

Description

RST is low, all the outputs are put in high impedance state and The IDT54/74FCT388915T uses phase-lock loop technol- registers at Q, Q and Q/2 outputs are reset.

ogy to lock the frequency and phase of outputs to the input The IDT54/74FCT388915T requires one external loop filter reference clock.

Datasheet Details

Part number	IDT74FCT388915T100
Manufacturer	Integrated Device Technology
File Size	145.69 KB
Description	3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)
Datasheet	IDT74FCT388915T100 Datasheet
Additional preview pages of the IDT74FCT388915T100 datasheet.

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Full PDF Text Transcription

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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES Integrated Device Technology, Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) IDT54/74FCT388915T 70/100/133/150 PRELIMINARY is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device. The PLL consists of • 0.5 MICRON CMOS Technology the phase/frequency detector, charge pump, loop filter and • Input frequency range: 10MHz – f2Q Max. spec VCO. The VCO is designed for a 2Q operating frequency (FREQ_SEL = HIGH) range of 40MHz to f2Q Max. • Max. output frequency: 150MHz The IDT54/74FCT388915T provides 8 outputs with 350ps • Pin and function compatible with FCT88915T, MC88915T skew.

Published: Apr 4, 2005 |