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IDT74FCT16601CT - FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

Download the IDT74FCT16601CT datasheet PDF. This datasheet also covers the IDT-74FCT variant, as both devices belong to the same fast cmos 18-bit universal bus transceiver with 3-state outputs family and are provided as variant models within a single manufacturer datasheet.

Description

FCT16601AT/CT/ET and ABT16601 for on-board bus interThe FCT16601AT/CT/ET and FCT162601AT/CT/ET 18- face applications.

Features

  • FCT16601AT/CT/ET: same transceiver.
  • High drive outputs (-32mA IOH, 64mA IOL) The FCT16601AT/CT/ET are ideally suited for driving.
  • Power off disable outputs permit “live insertion” high-capacitance loads and low-impedance backplanes. The.
  • Typical VOLP (Output Ground Bounce) < 1.0V at output buffers are designed with power off disable capability VCC = 5V, TA = 25°C to allow "live insertion" of boards when used as backplane.
  • Features for FCT162601AT/CT/ET: drive.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT-74FCT-16601AT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT74FCT16601CT
Manufacturer Integrated Device Technology
File Size 116.12 KB
Description FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Datasheet download datasheet IDT74FCT16601CT Datasheet

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Other Datasheets by Integrated Device Technology

Part Number Description
IDT74FCT16601AT FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
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Full PDF Text Transcription

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Integrated Device Technology, Inc. FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS IDT74FCT16601AT/CT/ET IDT74FCT162601AT/CT/ET PRODUCT PREVIEW bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit reg• Common features: istered bus transceivers combine D-type latches and D-type – 0.5 MICRON CMOS Technology flip-flops to allow data flow in either direction in a transparent, – High-speed, low-power CMOS replacement for latched or clocked mode. Each direction has an independent ABT functions latch enable, an independent clock with a clock enable, and an – Typical tSK(o) (Output Skew) < 250ps independent output enable. The package is organized with a – Low input and output leakage ≤1µ A (max.
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