Datasheet4U Logo Datasheet4U.com

IDT71V2558S - 3.3V Synchronous ZBT SRAMs 2.5V I/O

Download the IDT71V2558S datasheet PDF. This datasheet also covers the IDT71V2556S variant, as both devices belong to the same 3.3v synchronous zbt srams 2.5v i/o family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS.

They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT71V2556S_IntegratedDeviceTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71V2558S
Manufacturer Integrated Device Technology
File Size 578.14 KB
Description 3.3V Synchronous ZBT SRAMs 2.5V I/O
Datasheet download datasheet IDT71V2558S Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
IDT71V2556S 3.3V Synchronous ZBT SRAMs IDT
IDT71V2556SA 3.3V Synchronous ZBT SRAMs IDT
IDT71V2556XS 3.3V Synchronous ZBT SRAMs IDT
IDT71V2556XSA 3.3V Synchronous ZBT SRAMs IDT
IDT71V2546S 3.3V Synchronous ZBT SRAM IDT

Other Datasheets by Integrated Device Technology

Part Number Description
IDT71V2558SA 3.3V Synchronous ZBT SRAMs 2.5V I/O
IDT71V2546SA 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
IDT71V2548S 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
IDT71V2548SA 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
IDT71V256SA LOW POWER 3.3V CMOS FAST SRAM 256K

Full PDF Text Transcription

Click to expand full text
128K x 36, 256K x 18 3.3V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs 128K x 36, 256K x 18 memory configurations x Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) x ZBTTM Feature - No dead cycles between write and read cycles x Internally synchronized output buffer enable eliminates the need to control OE x www.DataSheet4U.com Single R/W (READ/WRITE) control pin x Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications x 4-word burst capability (interleaved or linear) x Individual byte write (BW1 - BW4) control (May tie active) x Three chip enables for simple depth expansion x 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ) x Optional - Boundary Scan JTAG Interface (IEEE 1149.
Published: |