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79RC32438 - IDTTM InterpriseTM Integrated Communications Processor

Download the 79RC32438 datasheet PDF. This datasheet also covers the 79RC32K438 variant, as both devices belong to the same idttm interprisetm integrated communications processor family and are provided as variant models within a single manufacturer datasheet.

Description

for EJTAG/JTAG pins in Table 1.

Changed DDRDM[7:0] from input/output to output only in Tables 1 and 2 and Logic Diagram.

Added new section, Voltage Sense Signal Timing, as part of EJTAG description.

Features

  • 32-bit CPU Core.
  • MIPS32 instruction set.
  • Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches.
  • 16 dual-entry JTLB with variable page sizes.
  • 3-entry instruction TLB www. DataSheet4U. com.
  • 3-entry data TLB.
  • Max issue rate of one 32x16 multiply per clock.
  • Max issue rate of one 32x32 multiply every other clock.
  • CPU control with start, stop and single stepping.
  • S.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (79RC32K438_IntegratedDeviceTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 79RC32438
Manufacturer Integrated Device Technology
File Size 714.94 KB
Description IDTTM InterpriseTM Integrated Communications Processor
Datasheet download datasheet 79RC32438 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
79RC32435 Communications Processor Renesas
79RC32332 IDT79RC32332 IDT
79RC32355 Communications Processor Renesas
79RC32364 RISController Embedded 32-bit Microprocessor IDT

Other Datasheets by Integrated Device Technology

Part Number Description
79RC32435 Communications Processor
79RC32334 IDT Interprise Integrated Communications Processor
79RC32351 IDT Interprise Integrated Communications Processor
79RC32355 Communications Processor
79RC32K438 Communications Processor

Full PDF Text Transcription

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IDTTM InterpriseTM Integrated Communications Processor 79RC32438 Features 32-bit CPU Core – MIPS32 instruction set – Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches – 16 dual-entry JTLB with variable page sizes – 3-entry instruction TLB www.DataSheet4U.com – 3-entry data TLB – Max issue rate of one 32x16 multiply per clock – Max issue rate of one 32x32 multiply every other clock – CPU control with start, stop and single stepping – Software breakpoints support – Hardware breakpoints on virtual addresses – Enhanced JTAG and ICE Interface that is compatible with v2.
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