M2006-12A Datasheet | Integrated Circuit Systems

DESCRIPTION The M2006-12A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. Clock multiplication ratios (including forward and inverse FEC) are pin-selected from pre-programming look-up tables. Includes Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV pliance during reference clock reselection. Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected. This phase-change triggered implementation of HS is not remended when using an unstable reference (more than 1ns jitter pk-to-pk) or when the resulting phase detector frequency is less than 5MHz. 28 29 30 31 32 33 34 35 36 (Top View) 18 17 16 15 14 13 12 11 10 P0_SEL P1_SEL n FOUT0 FOUT0 GND n FOUT1 FOUT1 VCC GND FEATURES - Reduced intrinsic output jitter and improved power supply noise rejection pared to M2006-12 - Similar to the M2006-02A - and pin-patible - but adds...