ICS95V860 Datasheet PDF - Integrated Circuit Systems 2.5V DDR/Zero Delay Fan Out Buffer Specs

ICS95V860 - 2.5V DDR/Zero Delay Fan Out Buffer

Datasheet Summary

Features

Low skew, low jitter PLL clock driver.
1 to 13 differential clock distribution (SSTL_2).
Feedback pins for input to output synchronization.
PD# for power management.
Spread Spectrum-tolerant inputs.
Auto PD when input signal removed.
0°C to 85°C operation Switching Characteristics:.
CYCLE - CYCLE jitter (>100MHz):.

Datasheet Details

Part number	ICS95V860
Manufacturer	Integrated Circuit Systems
File Size	107.59 KB
Description	2.5V DDR/Zero Delay Fan Out Buffer
Datasheet	ICS95V860 Datasheet
Additional preview pages of the ICS95V860 datasheet.

📁 Similar Datasheet

ICS95V842 - Clock Driver (Renesas)

ICS95V847 - Clock Driver (Renesas)

ICS95V857C - Clock Driver (Renesas)

ICS95V157 - 2.5V Single-Ended to SSTL_2 Clock Driver (Renesas)

ICS95V2F857A - 2.5V Wide Range Frequency Clock Driver (Renesas)

ICS95VLP857 - Clock Driver (Renesas)

ICS950201 - Programmable Timing Controller (Renesas)

ICS950202 - Programmable Timing Control Hub (Renesas)

ICS950220 - Programmable Timing Control Hub (Renesas)

ICS950401 - AMD System Clock (Renesas)

Full PDF Text Transcription

Click to expand full text

Integrated Circuit Systems, Inc. ICS95V860 2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) Recommended Application: DDR Memory Modules / Zero Delay Fan Out Buffer Product Description/Features: • Low skew, low jitter PLL clock driver • 1 to 13 differential clock distribution (SSTL_2) • Feedback pins for input to output synchronization • PD# for power management • Spread Spectrum-tolerant inputs • Auto PD when input signal removed • 0°C to 85°C operation Switching Characteristics: • CYCLE - CYCLE jitter (>100MHz):<75ps • OUTPUT - OUTPUT skew: <70ps • DUTY CYCLE: 49% - 51% Functionality INPUTS AVDD PD# GND GND 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.

Published: Mar 12, 2014 |