Datasheet4U Logo Datasheet4U.com

ICS8547 - 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS

Description

The ICS8547 is a Hex low skew, high performance 1-to-2 Differential-to-LVDS Clock Buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS.

Features

  • 12 LVDS outputs.
  • Selectable CLKx, nCLKx inputs.
  • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL.
  • Maximum output frequency: 700MHz.
  • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks.
  • Translates any single-ended input signal to LVDS with resistor bias on nCLKx input.
  • Output skew: 250ps (maximum).
  • Bank skew: 1.

📥 Download Datasheet

Datasheet Details

Part number ICS8547
Manufacturer Integrated Circuit Systems
File Size 144.06 KB
Description 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Datasheet download datasheet ICS8547 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS854104 Differential-to-LVDS Fanout Buffer Renesas
ICS85411I 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER Integrated Device Technology
ICS8543 Differential-to-LVDS Fanout Buffer Renesas
ICS8543I Differential-to-LVDS Fanout Buffer Renesas
ICS8543I Differential-to-LVDS Fanout Buffer Integrated Device Technology

Other Datasheets by Integrated Circuit Systems

Part Number Description
ICS85401 2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
ICS854058AG DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
ICS85408 TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

Full PDF Text Transcription

Click to expand full text
Integrated Circuit Systems, Inc. ICS8547 HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS FEATURES • 12 LVDS outputs • Selectable CLKx, nCLKx inputs • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks • Translates any single-ended input signal to LVDS with resistor bias on nCLKx input • Output skew: 250ps (maximum) • Bank skew: 15ps (maximum) • Part-to-part skew: 500ps (maximum) • Propagation delay: 1.8ns (maximum) • 3.
Published: |