IS42LS16800A Datasheet PDF - Integrated Circuit Solution 128-MBIT SYNCHRONOUS DRAM Specs

IS42LS16800A - 128-MBIT SYNCHRONOUS DRAM

Datasheet Summary

Description

A0-A11 A0-A8, A10 BA0, BA1 I/O0 to I/O7 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM VDD Vss VDDQ VssQ NC Write Enable x 8 Lower Bye, Input/Output Ma

Features

Clock frequency: 133 100, MHz.
Fully synchronous; all signals referenced to a positive clock edge.
Internal bank for hiding row access/precharge.
Power supply IS42LS81600A IS42LS16800A IS42LS32400A IS42S81600A IS42S16800A IS42S32400A.
LVTTL interface.
Programmable burst length.
(1, 2, 4, 8, full page).
Programmable burst sequence: Sequential/Interleave.
Extended Mode Register.
Programmable Power Reduction.

Datasheet Details

Part number	IS42LS16800A
Manufacturer	Integrated Circuit Solution
File Size	570.21 KB
Description	128-MBIT SYNCHRONOUS DRAM
Datasheet	IS42LS16800A Datasheet
Additional preview pages of the IS42LS16800A datasheet.

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Full PDF Text Transcription

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IS42S81600A, IS42LS81600A IS42S16800A, IS42LS16800A IS42S32400A, IS42LS32400A 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM FEATURES • Clock frequency: 133 100, MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42LS81600A IS42LS16800A IS42LS32400A IS42S81600A IS42S16800A IS42S32400A • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Extended Mode Register • Programmable Power Reduction Feature by partial array activation during Self-Refresh • Auto Refresh (CBR) • Temp. Compensated Self Refresh.

Published: Aug 2, 2011 |