M2006-12
DESCRIPTION
The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation. They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre-programming look-up tables. The M2006-12 adds Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV pliance during reference clock reselection. Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected.
This phase-change triggered implementation of HS is not remended when using an unstable reference (more than 1ns jitter pk-to-pk) or when the resulting phase detector frequency is less than 5MHz. Refer to full product data sheet for more information.
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M2006-02 M2006-12
(Top View)
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P0_SEL P1_SEL n FOUT0 FOUT0 GND n FOUT1 FOUT1 VCC GND
FEATURES
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