CYT4BB Key Features
- CPU subsystem
- Single-cycle multiply
- Single/double-precision floating point unit (FPU)
- 16-KB data cache, 16-KB instruction cache
- Memory protection unit (MPU)
- 16-KB instruction and 16-KB data tightly-coupled memories (TCM)
- Single-cycle multiply
- Inter-processor munication in hardware
- Three DMA controllers
- Peripheral DMA controller #0 (P-DMA0) with 100 channels
