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SEMD4
NPN/PNP Silicon Digital Transistor Array Preliminary data • Switching circuit, inverter, interface circuit, driver circuit • Two (galvanic) internal isolated NPN/PNP Transistors in one package • Built in bias resistor (R1=10kΩ) Tape loading orientation
Top View
3 2 1
4 5 3 6 1 2
Marking on SOT666 package (for example W R) corresponds to pin 1 of device Position in tape: pin 1 same of feed hole side
C1 6
B2 5
E2 4
R2 R1 TR1 R2 1 2 B1 3 C2
EHA07176
TR2 R1
4 5 6
Direction of Unreeling
Type SEMD4
Maximum Ratings Parameter
Collector-emitter voltage Collector-base voltage Emitter-base voltage Input on Voltage DC collector current Total power dissipation, TS = 75 °C Junction temperature Storage temperature
Thermal Resistance
Junction - soldering point 1)
1For calculation of R t
SEMD4 Datasheet
