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HYB25D256800BT - 256MBit Double Data Rata SDRAM

Download the HYB25D256800BT datasheet PDF. This datasheet also covers the HYB-25D variant, as both devices belong to the same 256mbit double data rata sdram family and are provided as variant models within a single manufacturer datasheet.

Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.

It is internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.

Features

  • CAS Latency and Clock Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400B DDR400A -5 -5A 133 133 166 200 200 200.
  • Double data rate architecture: two data transfers per clock cycle.
  • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for reads and is center-aligned with data for writes.
  • Differential clock inputs (CK and CK).
  • Four internal.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYB-25D-256160.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HYB25D256800BT
Manufacturer Infineon Technologies AG
File Size 522.55 KB
Description 256MBit Double Data Rata SDRAM
Datasheet download datasheet HYB25D256800BT Datasheet

Full PDF Text Transcription

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HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.9 Features CAS Latency and Clock Frequency CAS Latency 2 2.
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