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IS66WVQ4M4EDALL - 16Mb QUADRAM

Datasheet Summary

Description

The IS66/67WVQ4M4EDALL/BLL are integrated memory device containing 16Mb Pseudo Static Random Access Memory, using a self-refresh DRAM array organized as 2M words by 8 bits.

The device supports Quad DDR interface, which is compatible with JEDEC standard x4 xSPI Flash.

Features

  • Industry Standard Serial Interface - Quad DDR (x4 xSPI) Interface: Command (1 byte) =SDR Address (2-byte) & Data = DDR - Low Signal Counts :7 Signal pins (CS#, SCLK, DQSM, SIO0~SIO3).
  • High Performance - On chip ECC (chunk size = 4 bit): 1-bit correction and 2-bit detection - Double Data Rate (DDR) Operation: 200MHz (200MB/s) at 1.8V VCC (1) 133MHz (133MB/s) at 3.0V VCC - Source Synchronous Output signal during Read Operation (DQSM) - Data Mask during Write Operation (DQSM) - Configura.

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Datasheet Details

Part number IS66WVQ4M4EDALL
Manufacturer ISSI
File Size 927.74 KB
Description 16Mb QUADRAM
Datasheet download datasheet IS66WVQ4M4EDALL Datasheet
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Full PDF Text Transcription

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IS66WVQ4M4EDALL/BLL IS67WVQ4M4EDALL/BLL 16Mb QUADRAM with On Chip ECC 1.8V/3.0V SERIAL PSRAM MEMORY WITH 200MHZ QUAD DDR (X4 XSPI INTERFACE) PROTOCOL DATA SHEET IS66/67WVQ4M4EDALL/BLL 16Mb QUADRAM with On Chip ECC SERIAL PSRAM MEMORY WITH 200MHz QUAD DDR (x4 xSPI) Interface FEATURES  Industry Standard Serial Interface - Quad DDR (x4 xSPI) Interface: Command (1 byte) =SDR Address (2-byte) & Data = DDR - Low Signal Counts :7 Signal pins (CS#, SCLK, DQSM, SIO0~SIO3)  High Performance - On chip ECC (chunk size = 4 bit): 1-bit correction and 2-bit detection - Double Data Rate (DDR) Operation: 200MHz (200MB/s) at 1.8V VCC (1) 133MHz (133MB/s) at 3.
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