Datasheet4U Logo Datasheet4U.com

IS61QDP2B44M18A - 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Description

2Mx36 and 4Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interfa

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
IS61C1024 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C256 32K x 8 Low Voltage CMOS STATIC RAM Integrated Silicon Solution
IS61C25616 256K x 8 High Speed CMOS STATIC RAM Integrated Silicon Solution
IS61C25616AL 256K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDP2B44M18A1 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B44M18A2 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B41M18A 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B41M18A1 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B41M18A2 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61QDP2B44M18A/A1/A2 IS61QDP2B42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) DECEMBER 2014 FEATURES DESCRIPTION  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.
Published: |