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IS61QDP2B42M18A - 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Description

The 36Mb IS61QDP2B41M36A/A1/A2 and IS61QDP2B42M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.0 cycle read latency.
  • Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and contr.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDP2B42M18A1 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B42M18A2 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B42M36A 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B42M36A1 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
IS61QDP2B42M36A2 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

Full PDF Text Transcription

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IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) JANUARY 2015 FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.
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