IS61QDB251236C Datasheet PDF - ISSI 18Mb QUAD Synchronous SRAM Specs

IS61QDB251236C - 18Mb QUAD Synchronous SRAM

This page provides the datasheet information for the IS61QDB251236C, a member of the IS61QDB21M18C 18Mb QUAD Synchronous SRAM family.

Datasheet Summary

Description

The 18Mb IS61QDB251236C and IS61QDB21M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising ed.

Datasheet Details

Part number	IS61QDB251236C
Manufacturer	ISSI
File Size	929.02 KB
Description	18Mb QUAD Synchronous SRAM
Datasheet	IS61QDB251236C Datasheet
Additional preview pages of the IS61QDB251236C datasheet.

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Full PDF Text Transcription

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IS61QDB21M18C IS61QDB251236C 1Mx18, 512Kx36 18Mb QUAD (Burst 2) Synchronous SRAM JANUARY 2021 FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two output clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.

Published: Feb 17, 2024 |