IS61DDSB21M18C Datasheet PDF - ISSI 18Mb DDR-II SIO SYNCHRONOUS SRAM Specs

IS61DDSB21M18C - 18Mb DDR-II SIO SYNCHRONOUS SRAM

Datasheet Summary

Description

The 18Mb IS61DDSB251236C and IS61DDSB21M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a separate I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Features

512Kx36 and 1Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid window.
Seperate I/O read and write ports.
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two input clocks (C and.

Datasheet Details

Part number	IS61DDSB21M18C
Manufacturer	ISSI
File Size	954.42 KB
Description	18Mb DDR-II SIO SYNCHRONOUS SRAM
Datasheet	IS61DDSB21M18C Datasheet
Additional preview pages of the IS61DDSB21M18C datasheet.

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Full PDF Text Transcription

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IS61DDSB21M18C IS61DDSB251236C 1Mx18, 512Kx36 18Mb DDR-II (Burst 2) SIO SYNCHRONOUS SRAM APRIL 2016 FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip delay-locked loop (DLL) for wide data valid window.  Seperate I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two input clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.  HSTL input and output interface.

Published: Feb 18, 2024 |