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IS49NLC18160A - Common I/O RLDRAM 2 Memory

This page provides the datasheet information for the IS49NLC18160A, a member of the IS49NLC93200A Common I/O RLDRAM 2 Memory family.

Datasheet Summary

Description

1.1 288Mb (32Mx9) Common I/O BGA Ball-out (Top View) 1 2 3 4 56 7 8 9 10 11 12 A VREF VSS VEXT VSS VSS VEXT TMS TCK B VDD DNU3 DNU3 VSSQ VSSQ DQ0 DNU3 VDD C VTT DNU3 DNU3 VDDQ VDDQ DQ1 DNU3 VTT D A221 DNU3 DNU3 VSSQ VSSQ QK0# QK0 VSS E A212 DNU3 DNU3 VDD

Features

  • 533MHz DDR operation (1.067 Gb/s/pin data rate).
  • 38.4Gb/s peak bandwidth (x36 at 533 MHz clock frequency).
  • Reduced cycle time (15ns at 533MHz).
  • 32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total, each 32ms).
  • 8 internal banks.
  • Non-multiplexed addresses (address multiplexing option available).
  • SRAM-type interface.
  • Programmable READ latency (RL), row cycle time, and burst sequence length.
  • Balanced READ and WRITE latencie.

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Datasheet preview – IS49NLC18160A

Datasheet Details

Part number IS49NLC18160A
Manufacturer ISSI
File Size 1.18 MB
Description Common I/O RLDRAM 2 Memory
Datasheet download datasheet IS49NLC18160A Datasheet
Additional preview pages of the IS49NLC18160A datasheet.

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Full PDF Text Transcription

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IS49NLC93200A/IS49NLC18160A/IS49NLC36800A 32Mbx9, 16Mbx18, 8Mbx36 Common I/O RLDRAM 2 Memory AUGUST 2021 FEATURES  533MHz DDR operation (1.067 Gb/s/pin data rate)  38.4Gb/s peak bandwidth (x36 at 533 MHz clock frequency)  Reduced cycle time (15ns at 533MHz)  32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total, each 32ms)  8 internal banks  Non-multiplexed addresses (address multiplexing option available)  SRAM-type interface  Programmable READ latency (RL), row cycle time, and burst sequence length  Balanced READ and WRITE latencies in order to optimize data bus utilization  Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK.
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