Datasheet4U Logo Datasheet4U.com

IS46TR16512B - 8Gb DDR3 SDRAM

Datasheet Summary

Description

RAS#.

CAS#.

Features

  • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V.
  • Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V - Backward compatible to 1.5V.
  • High speed data transfer rates with system frequency up to 933 MHz.
  • 8 internal banks for concurrent operation.
  • 8n-Bit pre-fetch architecture.
  • Programmable CAS Latency.
  • Programmable Additive Latency: 0, CL-1,CL-2.
  • Programmable CAS WRITE latency (CWL) based on tCK.
  • Programmable Burst Le.

📥 Download Datasheet

Datasheet preview – IS46TR16512B

Datasheet Details

Part number IS46TR16512B
Manufacturer ISSI
File Size 3.73 MB
Description 8Gb DDR3 SDRAM
Datasheet download datasheet IS46TR16512B Datasheet
Additional preview pages of the IS46TR16512B datasheet.

📁 Similar Datasheet

  • IS46R16160F - 256Mb DDR SDRAM (Integrated Silicon Solution)
  • IS46R16320D - 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM (Integrated Silicon Solution)
  • IS46R16320E - 512Mb DDR SDRAM (Integrated Silicon Solution)
  • IS46R16800E - 128Mb DDR SDRAM (Integrated Silicon Solution)
  • IS46R32160D - 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM (Integrated Silicon Solution)
  • IS46R32160E - 512Mb DDR SDRAM (Integrated Silicon Solution)
  • IS46R32400E - 128Mb DDR SDRAM (Integrated Silicon Solution)
  • IS46R32800F - 256Mb DDR SDRAM (Integrated Silicon Solution)
  • IS46R86400D - 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM (Integrated Silicon Solution)
  • IS41C16100 - 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE (Integrated Silicon Solution)
Other Datasheets by ISSI

Full PDF Text Transcription

Click to expand full text
IS43/46TR16512B, IS43/46TR16512BL, IS43/46TR81024B, IS43/46TR81024BL 1Gx8, 512Mx16 8Gb DDR3 SDRAM FEATURES • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V • Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V - Backward compatible to 1.5V • High speed data transfer rates with system frequency up to 933 MHz • 8 internal banks for concurrent operation • 8n-Bit pre-fetch architecture • Programmable CAS Latency • Programmable Additive Latency: 0, CL-1,CL-2 • Programmable CAS WRITE latency (CWL) based on tCK • Programmable Burst Length: 4 and 8 • Programmable Burst Sequence: Sequential or Interleave • BL switch on the fly • Auto Self Refresh(ASR) • Self Refresh Temperature(SRT) JANUARY 2024 • Refresh Interval: 7.8 µs (8192 cycles/64 ms) Tc= -40°C to 85°C 3.
Published: |