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IS46R32800D - DDR SDRAM

This page provides the datasheet information for the IS46R32800D, a member of the IS43R32800D DDR SDRAM family.

Datasheet Summary

Description

x8 A0-A12 A0-A9 BA0, BA1 DQ0 DQ7 CK, CK CKE CS CAS RAS WE Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Column Address Strobe Command Row Address Strobe Command Write Enable DM DQS VDD VDDQ VSS VSSQ VREF NC Data Write Mas

Features

  • VDD and VDDQ: 2.5V ± 0.2V.
  • SSTL_2 compatible I/O.
  • Double-data rate architecture; two data transfers per clock cycle.
  • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs.
  • Differential clock inputs (CK and CK).
  • DLL aligns DQ and DQS transitions with CK transitions.
  • Commands ent.

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Datasheet preview – IS46R32800D

Datasheet Details

Part number IS46R32800D
Manufacturer ISSI
File Size 1.08 MB
Description DDR SDRAM
Datasheet download datasheet IS46R32800D Datasheet
Additional preview pages of the IS46R32800D datasheet.

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Full PDF Text Transcription

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IS43R83200D IS43/46R16160D, IS43/46R32800D JUNE 2012 8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation • Data Mask for write data.
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