IS46LR16160G Datasheet PDF - ISSI 4M x 16Bits x 4Banks Mobile DDR SDRAM Specs

IS46LR16160G - 4M x 16Bits x 4Banks Mobile DDR SDRAM

Datasheet Summary

Description

The IS43/46LR16160G is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 4,194,304 words x 16 bits.

This product uses a double-data-rate architecture to achieve high-speed operation.

The Data Input/ Output signals are transmitted on a 16-bit bus.

Features

JEDEC standard 1.8V power supply.
VDD = 1.8V, VDDQ = 1.8V.
Four internal banks for concurrent operation.
MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave).
Fully differential clock inputs (CK, /CK).
All inputs except data & DM are sampled at the rising edge of the system clock.
Data I/O transaction on both edges of data strobe.
Bidirectional da.

Datasheet Details

Part number	IS46LR16160G
Manufacturer	ISSI
File Size	1.19 MB
Description	4M x 16Bits x 4Banks Mobile DDR SDRAM
Datasheet	IS46LR16160G Datasheet
Additional preview pages of the IS46LR16160G datasheet.

📁 Similar Datasheet

IS46R16160F - 256Mb DDR SDRAM (Integrated Silicon Solution)

IS46R16320D - 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM (Integrated Silicon Solution)

IS46R16320E - 512Mb DDR SDRAM (Integrated Silicon Solution)

IS46R16800E - 128Mb DDR SDRAM (Integrated Silicon Solution)

IS46R32160D - 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM (Integrated Silicon Solution)

IS46R32160E - 512Mb DDR SDRAM (Integrated Silicon Solution)

IS46R32400E - 128Mb DDR SDRAM (Integrated Silicon Solution)

IS46R32800F - 256Mb DDR SDRAM (Integrated Silicon Solution)

IS46R86400D - 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM (Integrated Silicon Solution)

IS41C16100 - 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE (Integrated Silicon Solution)

Full PDF Text Transcription

Click to expand full text

IS43/46LR16160G 4M x 16Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR16160G is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 4,194,304 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

Published: Jun 28, 2016 |