IS45S16400J Datasheet PDF - ISSI SYNCHRONOUS DYNAMIC RAM Specs

IS45S16400J - SYNCHRONOUS DYNAMIC RAM

Datasheet Summary

Description

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits.

Internally configured as a quad-bank DRAM with a synchronous interface.

Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.

Features

Clock frequency: 200, 166, 143, 133 MHz.
Fully synchronous; all signals referenced to a positive clock edge.
Internal bank for hiding row access/precharge.
Single 3.3V power supply.
LVTTL interface.
Programmable burst length.
(1, 2, 4, 8, full page).
Programmable burst sequence: Sequential/Interleave.
Self refresh modes.
Auto refresh (CBR).
4096 refresh cycles every 64 ms (Com, Ind, A1 grade) or 1.

Datasheet Details

Part number	IS45S16400J
Manufacturer	ISSI
File Size	1.14 MB
Description	SYNCHRONOUS DYNAMIC RAM
Datasheet	IS45S16400J Datasheet
Additional preview pages of the IS45S16400J datasheet.

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Full PDF Text Transcription

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IS42S16400J IS45S16400J 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEBRUARY 2022 FEATURES • Clock frequency: 200, 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.

Published: May 12, 2014 |