IS45R83200D Datasheet PDF - ISSI 256-MBIT SYNCHRONOUS DRAM Specs

IS45R83200D - 256-MBIT SYNCHRONOUS DRAM

This page provides the datasheet information for the IS45R83200D, a member of the IS42R83200D 256-MBIT SYNCHRONOUS DRAM family.

Datasheet Summary

Description

A0-A12 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command WE DQM Vdd Vss Vddq Vssq NC Wri

Features

Clock frequency: 133, 100 MHz.
Fully synchronous; all signals referenced to a positive clock edge.
Internal bank for hiding row access/precharge.
Single Power supply: 2.5V + 0.2V.
LVTTL interface.
Programmable burst length.
(1, 2, 4, 8, full page).
Programmable burst sequence: Sequential/Interleave.
Auto Refresh (CBR).
Self Refresh.
8K refresh cycles every 16 ms (A2 grade) or 64 ms (com.

Datasheet Details

Part number	IS45R83200D
Manufacturer	ISSI
File Size	926.82 KB
Description	256-MBIT SYNCHRONOUS DRAM
Datasheet	IS45R83200D Datasheet
Additional preview pages of the IS45R83200D datasheet.

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Full PDF Text Transcription

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IS42R83200D, IS42R16160D IS45R83200D, IS45R16160D 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM MARCH 2010 FEATURES • Clock frequency: 133, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 2.5V + 0.

Published: Aug 1, 2016 |