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IS43R16400B - Four internal banks for concurrent operation

Datasheet Summary

Description

A0-A11 A0-A7 BA0, BA1 DQ0 DQ15 CK, CK CKE CS CAS RAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Column Address Strobe Command Row Address Strobe Command WE LDM, UDM LDQS, UDQS VDD VDDQ VSS VSSQ VREF NC Write Enable Data

Features

  • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) VDD and VDDQ: 2.6V ± 0.1V (-4) SSTL_2 compatible I/O Double-data rate architecture; two data transfers per clock cycle Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs Differential clock inputs (CK and CK) DLL aligns DQ and DQS transitions with CK transitions Comma.

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Datasheet Details

Part number IS43R16400B
Manufacturer ISSI
File Size 5.70 MB
Description Four internal banks for concurrent operation
Datasheet download datasheet IS43R16400B Datasheet
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Full PDF Text Transcription

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IS43R16400B 4Mx16 64Mb DDR SDRAM FEATURES • • • • • VDD and VDDQ: 2.5V ± 0.2V (-5, -6) VDD and VDDQ: 2.6V ± 0.1V (-4) SSTL_2 compatible I/O Double-data rate architecture; two data transfers per clock cycle Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs Differential clock inputs (CK and CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Four internal banks for concurrent operation Data Mask for write data.
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